=EF=BB=BF

Hi Patr= ick. I mean sometime between the 6th and 12th of August. I am not sur= e of the exact day yet

O= n Jul 31, 2025, at 9:12=E2=80=AFPM, Patrick Wong <patrick.nwtec@gmail.com= > wrote:

=EF=BB=BF
Hi Craig.

Good to he= ar from you. If you mean tomorrow, August 1, unfortunately, I'm in Ranc= ho Cordova helping out my family. Will return by Wednesday, Aug 6.&nbs= p;

If you mean September, yes i should be available.=

Let me know. Thanks.

Patrick

On T= hu, Jul 31, 2025 at 8:43=E2=80=AFPM SBC-85 <craig@sbc-85.com> wrote:
Hi Patrick, will you be around the first of next month so I can pick up t= hose things i forgot?

On= Feb 19, 2025, at 9:00=E2=80=AFAM, Patrick Wong <patrick.nwtec@gmail.com> wrote:<= br>
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Hi Craig,

I'll let you know if I find an= y info on this or if I find this board.

Best regard= s,

Patrick Wong
Northwest Technical Inc.
16920 Old County Road<= br>Brookings, OR 97415
Tel: 541-469-6644
Email: patrick.nwtec@gmail.com
= Website: www.multibus-international.com

On Tue, Feb 18, 2025 a= t 5:05=E2=80=AFPM <= craig@sbc-85.com> wrote:
Hi Patric= k

Made it back to Vancouver, thanks for meeting me yesterday and t= aking care of that chassis & MDS-800 cover until I get a chance to come b= ack down. That chassis will fit in my little airplane but the MDS-800 w= ould be a tight squeeze.
&nbs= p;
Here is the catalog cut sheet and a phot= ograph of the MDS-ROM simulator board. Please let me know if you come a= cross any information on them. I have the boards running from the MDS s= ide, i.e., I have access to the onboard RAM and the next step is to start re= verse engineering the interface for the device under test. One thing I= am trying to figure out first is this business of the operating modes you s= ee in the silkscreen on the board in a couple of places. Any idea what= Mode 18 and Mode M could mean? I have never seen intel use that termi= nology before. These boards were designed so you could have up to four= of them in a system and continue the memory from one board to the next.&nbs= p; =46rom the MDS perspective, you set the high address nibble in the jumper= s in the bottom left plus which board of the four this board is which set th= e next two address lines down. =46rom the device under test side, the m= emory could be byte wide or multi-byte and I am guessing that is where the M= ode 18 or mode M comes in. in the top right corner the user rom is set= in octal or it is set to Mode M. At this point I am guessing th= at mode 18 is when the boards were accessed individually for byte-wide memor= y and Mode M is when all boards were accessed simultaneously for 32-bit wide= access.

Any insight would be appreciated.

Thanks
craig
=