Envelope-to: craig@sbc-85.com
Delivery-date: Wed, 19 Feb 2025 11:00:24 -0600
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From: Patrick Wong <patrick.nwtec@gmail.com>
Date: Wed, 19 Feb 2025 09:00:00 -0800
Message-ID: <CAFwUL1+bY+U5+GcErQhZwTMGJ2uGhzfnVxBwtqtLHL_13=LaLA@mail.gmail.com>
Subject: Re: MDS-ROM-SIM-100
To: craig@sbc-85.com
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Hi Craig,

I'll let you know if I find any info on this or if I find this board.

Best regards,

Patrick Wong
Northwest Technical Inc.
16920 Old County Road
Brookings, OR  97415
Tel: 541-469-6644
Email: patrick.nwtec@gmail.com
Website: www.multibus-international.com


On Tue, Feb 18, 2025 at 5:05=E2=80=AFPM <craig@sbc-85.com> wrote:

> Hi Patrick
>
>
>
> Made it back to Vancouver, thanks for meeting me yesterday and taking car=
e
> of that chassis & MDS-800 cover until I get a chance to come back down.
> That chassis will fit in my little airplane but the MDS-800 would be a
> tight squeeze.
>
>
>
> Here is the catalog cut sheet and a photograph of the MDS-ROM simulator
> board.  Please let me know if you come across any information on them.  I
> have the boards running from the MDS side, i.e., I have access to the
> onboard RAM and the next step is to start reverse engineering the interfa=
ce
> for the device under test.  One thing I am trying to figure out first is
> this business of the operating modes you see in the silkscreen on the boa=
rd
> in a couple of places.  Any idea what Mode 18 and Mode M could mean?  I
> have never seen intel use that terminology before.  These boards were
> designed so you could have up to four of them in a system and continue th=
e
> memory from one board to the next.  From the MDS perspective, you set the
> high address nibble in the jumpers in the bottom left plus which board of
> the four this board is which set the next two address lines down.  From t=
he
> device under test side, the memory could be byte wide or multi-byte and I
> am guessing that is where the Mode 18 or mode M comes in.  in the top rig=
ht
> corner the user rom is set in octal or it is set to  Mode M.  At this poi=
nt
> I am guessing that mode 18 is when the boards were accessed individually
> for byte-wide memory and Mode M is when all boards were accessed
> simultaneously for 32-bit wide access.
>
>
>
> Any insight would be appreciated.
>
>
>
> Thanks
>
> craig
>

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<div dir=3D"ltr">Hi Craig,<div><br></div><div>I&#39;ll let you know if I fi=
nd any info on this or if I find this board.</div><div><br></div><div>Best =
regards,<br><br>Patrick Wong<br>Northwest Technical Inc.<br>16920 Old Count=
y Road<br>Brookings, OR =C2=A097415<br>Tel: 541-469-6644<br>Email: <a href=
=3D"mailto:patrick.nwtec@gmail.com">patrick.nwtec@gmail.com</a><br>Website:=
 <a href=3D"http://www.multibus-international.com">www.multibus-internation=
al.com</a></div><div><br></div></div><br><div class=3D"gmail_quote gmail_qu=
ote_container"><div dir=3D"ltr" class=3D"gmail_attr">On Tue, Feb 18, 2025 a=
t 5:05=E2=80=AFPM &lt;<a href=3D"mailto:craig@sbc-85.com">craig@sbc-85.com<=
/a>&gt; wrote:<br></div><blockquote class=3D"gmail_quote" style=3D"margin:0=
px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><=
div class=3D"msg-8785947042725495667"><div lang=3D"EN-US" style=3D"overflow=
-wrap: break-word;"><div class=3D"m_-8785947042725495667WordSection1"><p cl=
ass=3D"MsoNormal">Hi Patrick<u></u><u></u></p><p class=3D"MsoNormal"><u></u=
>=C2=A0<u></u></p><p class=3D"MsoNormal">Made it back to Vancouver, thanks =
for meeting me yesterday and taking care of that chassis &amp; MDS-800 cove=
r until I get a chance to come back down.=C2=A0 That chassis will fit in my=
 little airplane but the MDS-800 would be a tight squeeze.<u></u><u></u></p=
><p class=3D"MsoNormal"><u></u>=C2=A0<u></u></p><p class=3D"MsoNormal">Here=
 is the catalog cut sheet and a photograph of the MDS-ROM simulator board.=
=C2=A0 Please let me know if you come across any information on them.=C2=A0=
 I have the boards running from the MDS side, i.e., I have access to the on=
board RAM and the next step is to start reverse engineering the interface f=
or the device under test.=C2=A0 One thing I am trying to figure out first i=
s this business of the operating modes you see in the silkscreen on the boa=
rd in a couple of places.=C2=A0 Any idea what Mode 18 and Mode M could mean=
?=C2=A0 I have never seen intel use that terminology before.=C2=A0 These bo=
ards were designed so you could have up to four of them in a system and con=
tinue the memory from one board to the next.=C2=A0 From the MDS perspective=
, you set the high address nibble in the jumpers in the bottom left plus wh=
ich board of the four this board is which set the next two address lines do=
wn.=C2=A0 From the device under test side, the memory could be byte wide or=
 multi-byte and I am guessing that is where the Mode 18 or mode M comes in.=
=C2=A0 in the top right corner the user rom is set in octal or it is set to=
 =C2=A0Mode M.=C2=A0 At this point I am guessing that mode 18 is when the b=
oards were accessed individually for byte-wide memory and Mode M is when al=
l boards were accessed simultaneously for 32-bit wide access.<u></u><u></u>=
</p><p class=3D"MsoNormal"><u></u>=C2=A0<u></u></p><p class=3D"MsoNormal">A=
ny insight would be appreciated.<u></u><u></u></p><p class=3D"MsoNormal"><u=
></u>=C2=A0<u></u></p><p class=3D"MsoNormal">Thanks<u></u><u></u></p><p cla=
ss=3D"MsoNormal">craig<u></u><u></u></p></div></div></div></blockquote></di=
v>

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