=EF=BB=BF=

Hi Craig,

I=E2=80=99m sorry I haven=E2=80=99t emailed you lately. I have been swa= mped with trying to get other projects that make money completed. I=E2=80=99= m heading to Indiana for my robot thing with automated sprinklers and water m= oisture sensors. I may work on the bubble memory for a day or so before I leave but it=E2=80=99s gonna be frozen until after Sep= tember.

Have you had any chance or any luck with the bubble memories from Polan= d?

Are you interested in keeping up with me on the core memory? I am also b= uilding a high-speed DSP and FFT hardware board and data collector for anima= l sounds in a grass field next to a forest from the frequency ranges of 20 H= z to 212 KHz. The sound made by the animals in the field and forest indicate what seasons of animals exi= st. This is used for determining if the forest or field is out of succession= that is possible to grow ginseng. This is what I do in Indiana. I=E2=80=99l= l save the coefficient of the magnitude of each frequency and is change in time onto a 1 TB hard drive that is conn= ected to my embedded processors.

I=E2=80=99ve tried connecting to the gentleman using the bubble memory.= I needed to get an account and something happened. It was hard for me to le= ave a message.

Sent from my iPhone

On Jul 17, 2023, at 4:04 PM, craig@sbc-85.com wrot= e:

=EF=BB=BF

so you are getting the same sequence of 120 bytes and= then they repeat?

if the number of channels in the block length registe= r were wrong, you would lose bubble data but I do not think the boot loop da= ta would be incorrect and certainly not be just 1/3 of a 120 byte sequence.&= nbsp;

if you are reading the bootloop, then the starting ad= dress of the data read doesn=E2=80=99t matter.

as long as the INIT completes successfully, then the b= ootloop is in the FSA. you have already been able to reliably read the bootl= oop from the FSA. so unless there is some intermittent flakeyness in y= our circuit or software, I can=E2=80=99t think of what this repeating bootloop data means

From: Paul Holowko <pholowko@hotmail.com>= ;
Sent: Monday, July 17, 2023 3:35 PM
To: craig@sbc-85.com
Subject: Re: Bubble memory questions (finally got boot number)

I keep d= oing an init, add parameters, command "1b" or "B" and it seems to be r= eading different places in memory.. If it do it for three times,= it keeps repeating the same three sets of 40 numbers. Even if I turn off the board and repower it up. The same three sets o= f numbers.

&nb= sp;

&nb= sp;

&nb= sp;

From: craig@sbc-85.com <craig@sbc-85.com>
Sent: Monday, July 17, 2023 10:05 PM
To: 'Paul Holowko' <pholow= ko@hotmail.com>
Subject: RE: Bubble memory questions (finally got boot number)=

yes, that is what I meant. I only have 7110 le= adless carrier versions built. I had a 7110A(Z) version but I can=E2=80= =99t lay my hands on it for some reason.

From: Paul Holowko <pholowko@hotmail.com>
Sent: Monday, July 17, 2023 2:35 PM
To: craig@sbc-85.com
Subject: Re: Bubble memory questions (finally got boot number)

they ar= e AZs

From: craig@sbc-85.com <craig@sbc-85.com>
Sent: Monday, July 17, 2023 9:26 PM
To: 'Paul Holowko' <pholow= ko@hotmail.com>
Subject: RE: Bubble memory questions (finally got boot number)=

indeed, that is a breakthrough.

Turns out that I don=E2=80=99t have a 7110A version= of the board so I had to get some parts on order so I can test the Polish b= ubble chips.

regards

craig

From: Paul Holowko <pholowko@hotmail.com>
Sent: Monday, July 17, 2023 8:57 AM
To: craig@sbc-85.com
Subject: Bubble memory questions (finally got boot number)=

Hi Cra= ig,

=

Thank y= ou so much. I just got the first bootloop back from a BMB.&n= bsp; It matched the label on the BMB!!!!! This helps a lot. Now I= 'm getting comfortable that the hardware is working. One of the four BMB from Poland worked. The other three had mixed results.&n= bsp; Two would not "init" and the other one that did "init" had the wrong bootloop number. It's tim= e to learn how to put the bootloop number back in. = I also think the connector I'm using for the BMB is too loose. I= find the one that fits tighter works consistently. The fifth BMB I or= dered with some support chips for $75 from Washington "init"s, but the bootloop number is all= wrong.

=

When t= he BMB do "init", they give a consistent wrong bootloop number. I'll f= irst get the loose connector to work and check if more will "init". If= the bootloop is wrong, I'll try re-write using the directions

=

&= lt;image001.png>

=

If tha= t bombs, then reseed. Need to get one more part and the little board i= s complete. If the seed and bootloop re-write does not work, dissectio= n.

=

When I= asked about how slow this device is, I was not asking about read and write s= peeds, but more about the access times for the whole system to read a page o= r so. It really was not a question, but more a comment about the speed of the technology. Old times......=

=

I have= at least one that works!!!!!!!!!!!!!

=

From: craig@sbc-85.com <craig@sbc-85.com>
Sent: Sunday, July 16, 2023 11:00 PM
To: 'Paul Holowko' <pholow= ko@hotmail.com>
Subject: RE: Bubble memory questions

I am looking at this again=E2=80=A6. did fixing th= e signal connection issues resolve the reading bootloop problem (not matchin= g the device)?

without a bubble installed, you are able to send a= bootloop to the FSA and read that bootloop data back correctly? but with a b= ubble installed you are doing the read but not getting the label data?<= /o:p>

the bootloop should be transferred from the bubble= into the FSA during the init command and if you have successfully read the f= ake bootloop from the FSA before inserting the bubble this could be a bubble= problem. is this one of the Polish bubbles? I purchased some of those last month that I have not g= otten around to testing yet so I am not sure of their integrity.

From: Paul Holowko <pholowko@hotmail.com>
Sent: Saturday, July 15, 2023 1:05 PM
To: craig@sbc-85.com
Subject: Re: Bubble memory questions

Hi Craig,

More updates. I can get a consultant bootloo= p map read. It does not match the label on top of the BM. Here is what I=E2=80= =99m getting=E2=80=A6=E2=80=A6.

<image002.jpg>

<image003.j= pg>
<image004.jpg>

Sent from my iPhone

On Jul 14, 2023, at= 3:58 PM, Paul Holowko <pholowko@= hotmail.com> wrote:

=EF=BB=BF Yes, it does write and read boot loop re= gister. It does work and i see the right signals. I=E2=80=99m now writing ro= utines that interface with 7220. The BMC is like a over grown sequential sta= te machine. I=E2=80=99m changing gears how I think about writing routines.

I=E2=80=99m finding I have small stupid stuff happ= ening. Like RAC 0F always has the highest bit set one for some reason when I= read the register. I write a 0x55 and get back a 0x95. I had a bad I/O port= on my cpu.

I send the command 0x11 unit and the status comes b= ack 0x81. I always wait for the busy to go low before another command, excep= t when fifo is one.

When I read the fifo, I get 0xFF. 0xFF 0x00 0x80 a= nd the rest is zeros

Sent from my iPhone

On Jul 8, 2023, at 9= :12 PM, craig@sbc-85.com wrote:

=EF=BB=BF

with the dummy module installed in place of the 71= 10, can you write and read the bootloop register in the 7242?
=
that will tell you if you have good communication b= etween the 7220 and the 7242

From: Paul Holowko <pholowko@hotmail.com>
Sent: Saturday, July 8, 2023 8:55 PM
To: craig@sbc-85.com
Subject: Re: Bubble memory questions

Yes, thank you. I meant 2. But let me double check= And yes, I can write and read the fifo. That worked right off the bat= . And i get 0x41 and at times 42.

Since I have not seen any Swap signals, my wanderi= ng if I erased the MBM. However, I=E2=80=99m still getting all 0XFF back. Le= t me double check on the FSA number.

Here=E2=80=99s the sequence:

Command 1B to set address in rac

Data to rac.BLR LSB. I 0x10

BLR MSB. 0x01

0x08

Address. 0x00

0x00

Stuff fifo with 68 bytes

Command 0x13. Page write

0x12. Page read. And I see waveforms on pin 3=

Read fifo

Dump to screen.

It comes up all 0xFF

Sent from my iPhone

On Jul 8, 2023, at 8= :24 PM, craig@sbc-85.com wrote:

=EF=BB=BF

Hi Paul,

the first step should be writing to the controller= with just the dummy module in place and see if you get back whatever data y= ou write to the FIFO. Are you able to do that so you know that you hav= e communication with the 7220?

then you should make sure that after you populate t= he registers that the status value returned shows that the operation has suc= cessfully completed, so the status should be 0x40 usually or maybe 0x41 or 0= x42. you should be able to do that without the bubble or the FSA installed.

when you say you have it configured for 1 FSA, do y= ou mean 2 FSA channels or did you actually set the parameter for 1 channel s= o it is only using two quads inside the bubble?

as for timing between the 7230 and 7242, I have ne= ver looked at that. as long as everything is connected properly, I hav= e not had the need to see what is going on between those two.
=

From: Paul Holowko <pholowko@hotmail.com>
Sent: Saturday, July 8, 2023 5:26 PM
To: craig@sbc-85.com
Subject: Re: Bubble memory questions

When I write to the BMB, i=E2=80=99m using the 13 c= ommand. Or =E2=80=9C3=E2=80=9D. I have set up the BLR for one FSA and for on= e page. That means I enter in 68 bites of something and then give the three c= ommand. When I do a page read, I get 68 bites of all 0xFF. =E2=80=9C0x12=E2=80=9D I=E2=80=99m assuming this has something to do w= ith my timing not occurring between the 7230 and the 7242. I do see a clock a= nd I/O data going between the 7220 and the 7242.

I do see 12 V pulsing up and down on the coils ins= ide the BMB

Sent from my iPhone

On Jul 8, 2023, at 1= 0:35 AM, craig@sbc-85.com wrote:

=EF=BB=BF

You may be interested in his bubble videos also

Magnetic Bubble Memory Storage on a Heathkit H8 - YouT= ube

From: Paul Holowko <pholowko@hotmail.com>
Sent: Thursday, July 6, 2023 9:21 PM
To: craig@sbc-85.com
Subject: Re: Bubble memory questions

I took a break today from the BM. Worked on an air= filter for smoke and respiratory issues. Lit up a neon sign. Calculated the= voltage and ratios to produce around 8000 volts. The core is specific for u= p to 200KHz.

<image005.j= pg>
<image006.jpg>
<image007.jpg>
<image008.jpg>

Sent from my iPhone

On Jul 6, 2023, at 8= :42 PM, Paul Holowko <pholowko@ho= tmail.com> wrote:

=EF=BB=BF Thank you= for doing this. It=E2=80=99s really helping. I now understand what yo= u were trying to do. The next question is the reseeding schematic. I=E2=80=99= m confused which socket, I=E2=80=99m assuming on the right, gets all of the connections. Are all the pins between the header and the socket on t= he right?

Sent from my iPhone

On Jul 6, 2023, at 7= :58 PM, craig@sbc-85.com wrote:

=EF=BB=BF

updated user=E2=80=99s manual with pictures of int= el reseed=E2=80=A6 but that isn=E2=80=99t overly helpful until I build the r= eproduction and update the manual again

From: c= raig@sbc-85.com <craig@sbc-85.com= >
Sent: Thursday, July 6, 2023 7:33 PM
To: 'Paul Holowko' <pholow= ko@hotmail.com>
Subject: RE: Bubble memory questions

I see, thanks for pointing this all out. I f= orgot that I did the layout side by side rather than over-under like the Int= el version. the left side, where it plugs into the bubble board, DIP h= eader pins should be mounted to the bottom, not a normal socket. KiCAD didn=E2=80=99t have one of these so I just= used a socket in the model. I will build one and replace the photogra= phs in the manual. In the mean time, I have updated the manual with ad= ditional description and the reseed instructions as well as a possible part number for the DIP adapter pin. I use these s= ort of adapters from CNC tech available at digikey PN 1175-1524-5-ND

IC Sockets Products | IC Sock= et Adapters (cnctech.us)

let me get back to you on the page writing

From: Paul Holowko <pholowko@hotmail.com>
Sent: Thursday, July 6, 2023 6:42 PM
To: SBC-85 <craig@sbc-85.com>
Subject: Re: Bubble memory questions

=EF=BB=BF

Yes, I= have the instructions. My confusion is around the layout of the resee= ding board. The Intel reseed board seems different than the one you ma= de. Two sockets vs. one socket.

= ;

I am a= lso confused on page writing. I understand each page is 40 bytes, but how do= multi pages? I=E2=80=99m still figuring out the 68 thing<= /o:p>

= ;

= ;

= ;

= ;

From: SBC-85 <craig@sbc-85.com>
Sent: Thursday, July 6, 2023 5:59 PM
To: Paul Holowko <p= holowko@hotmail.com>
Subject: Re: Bubble memory questions

Do you have the Intel instructions on using the re= seed board? I have not reseeded in many years and have forgotten the d= etails.

I can scan the instructions and send to you if you= do not have them already.

I am out today, so tonight or tomorrow <= /o:p>

On Jul 5, 2023, at 9= :50 PM, Paul Holowko <pholowko@ho= tmail.com> wrote:

=EF=BB=BF I would l= ove the pictures. I need to see how the 7230 is plugged in your board and th= en how is it plugged into the memory board. I have tried to find pictu= res of it on the internet, but the internet is becoming obsolete.

Sent from my iPhone

On Jul 5, 2023, at 8= :04 PM, SBC-85 <craig@sbc-85.com&= gt; wrote:

=EF=BB=BF

Hi Paul,

That is unfortunate.

Read and write cycles are 4 clock cycles plus some= change. Figure 5 clock cycles to be safe, so 1250 ns total cycle time= .

I will send pics of my reseed module, hopefully to= morrow. I only have the one that comes with the intel BPK engineering k= it. I made my reproduction ones from reverse engineering that one. It i= s possible that there is a mistake on the reseed module.

Regards

Craig

On Jul 4, 2023, at 1= 0:48 PM, Paul Holowko <pholowko@h= otmail.com> wrote:

=EF=BB=BF

=EF=BB=BF

I think I made a mistake. The bubble is a AZ versi= on and I did not lift up pin 13. It looks like the whole MBM is erased. I=E2= =80=99m fairy sure the boot number is gone. The timing error flag reports 1 a= ll the time.

How fast does the BMC execute commands? It=E2= =80=99s at 4MHz, but my CPU is at 48 MHz. :-/

I=E2=80=99m making OS commands that are command sc= ripts for the BMC. These will turn into commands triggered by hardware from t= he the backplane connection.

Can you please send me a real picture of your seed= ing board with parts. I=E2=80=99m a bit confused.

I=E2=80=99m combing the manuals and bit by bit lea= rning details about the BM. It just takes time.

Sent from my iPhone

On Jul 1, 2023, at 4= :49 AM, Paul Holowko <pholowko@ho= tmail.com> wrote:

=EF=BB=BF Hi Craig,

The whole SN75463 business looks like it was desig= ned by a committee. I=E2=80=99m guessing it does not work on my board becaus= e there is a juicy inverter from your RESET. I was trying to avoid lea= rning the circuit; well, too late. It must have been designed by ex-HAM radio operators. Who uses 914s other then core memo= ry or crystal radios? Lol.

The interface is designed from scratch. It=E2=80=99= s an old architecture used inside the 4040 and 4004. I find computers/CPUs a= re not good at math or calculations, but rather moving data around. Hence, c= ore memory needs to have stuff done to it for it to stock pile data. The same goes for bubble and flash. The= board on the left directly connects the 7220 fifo to the back plane connect= or; chips are not populated, yet. The CPU on that board bit-bangs the 7220 R= D signals and handles data traffic.

The original plan is to use the bubble memory as a= really slow NVRAM where it stored tokens/symbols for an embedded compiler b= etween OP codes and micro-codes. The core memory would be a stack and intern= al regulators. Then build another compiler between OP codes and some form of computer language like C. Hence t= he running 1970s and 1980s joke, YACC. I=E2=80=99ve done this for my embedde= d composting machines.

I need all of the data storage devices to talk in t= he same way to each other. The common denominator appears to be Address and D= ata lines with RD and WR signals. The microcode is saved In EEPROMs where th= e output data are the control signals for the whole backplane system. Data and program are mixed on= a hardware level. It=E2=80=99s kind of C++ meets RISC.
=

This makes it possible= to run an FFT, solve differential equations or factor Taylor Series o= perations on an OP code/microcode level.

I=E2=80=99m putting I2C FRAM in the system too. Le= t=E2=80=99s face it, the whole system made with three different irons. = ;Sounds like a Julia Child recipe. Lol

Paul

Sent from my iPhone

On Jun 30, 2023, at= 9:00 PM, SBC-85 <craig@sbc-85.com> wrote:

=EF=BB=BF

=EF=BB=BF

Hi Paul,

Sorry I didn=E2=80=99t get back to you. When the w= eather is nice I am not at home much.

Pretty exciting that you have the board up, there i= s just something about using these things. Much like your core project= s. I have thought about doing something with core memory, but I really don't= have a particular fondness for it like I do bubble.

On my circuit, the 75463 output is pulled up and b= iased via R17, CR1, and R8. I think I lifted that from intel, it doesn= =E2=80=99t look like my style.

So your bubble board is from scratch? I would gues= s that there may be some people interested in it because it uses a straightf= orward connector like Intel=E2=80=99s original bubble kit making it easier t= o hang on other projects (easier than my finger connector on my SBC-85 board). I think there would also be peo= ple interested if you did a hackaday or YouTube video also.

I am out this weekend and next week depends on whe= ther if I am back at home working on electronics.

Congratulations on your success, I hope working th= e wires for the cores doesn=E2=80=99t make you too cross-eyed
=

Craig

On Jun 30, 2023, at= 8:39 PM, Paul Holowko <pholowko@= hotmail.com> wrote:

=EF=BB=BF Just wanted to let you know the bubble m= emory board is powered and I spent this afternoon building the OS to talk wi= th the BMC. Your samples and explanations really helped.

I used your circuits for the power down enable. Th= e RC does not work out too well with the 2 ms delay. And I had trouble with S= N75463. It seems to need pull-ups since it=E2=80=99s open collector.&n= bsp;

<image0.jpeg>

<image1.jpeg>

The board on the left is a PIC18F4550. It talks through USB to the computer.= I guess this can be a 1 Meg byte memory stick. Lol. The interface is one 74= act245 between the 7220 and the PIC. The board on the left connects into a b= ack plane.

I was thinking about using it on the farm, but it d= raws too much power. Just chips powered with out memory bubbling, it=E2=80=99= s 1/4 amp.

It wouldn=E2=80=99t be hard to get this to work wi= th configuration memory for some independent project. Currently I=E2=80=99m u= sing I2C FRAM. Not sure what to do with it. It is fun to build. <= o:p>

Thanks for listening. I=E2=80=99m off to put toget= her some core memory.

Sent from my iPhone

On Jun 27, 2023, at= 10:48 AM, Paul Holowko <pholowko= @hotmail.com> wrote:

=EF=BB=BF

Hi Cr= aig,

= ;

Thank= s for helping with the registration. I never got a registration e= mail. Can you please send a link where you are logging in? I'm a= lso getting a few 404 pages. I used to have webpages, but I gave that up. Currently, I'm automating a wasabi farm in Muncie= Indiana. We grow Wasabi by geothermal, wind and solar. It's tot= ally off the bridge. The local University has their EE and Computer EE= Juniors and Seniors over for a 2 hour lecture every time I'm there.

= ;

No, t= he board is not running with a CPU, but has been powered up for finding shor= ts and stupid things. The CPU boards come tomorrow and I'll stu= ff it right away. I hope there aren't too many problems getting is up and running. I'm more worried about bad c= hips. I have all of the parts so far. And I have plans for this b= ubble memory. Later......

= ;

The c= ore boards are from a PDP-8. I'm making the drivers from scratch. = ; I have the H-bridges going, but the core "fabric" is a little bit damaged f= rom removal or by age through the years. The PDP-8 cores are stacked together, so one driver runs all of the X and Y= for all the bits in a byte. I'm using the inhibit for making zeros.&n= bsp; It's been difficult to find information on this subject anymore on the i= nternet. The internet is getting more broken daily. I'm running the board at 2MHz on a countdown one-hot-st= ate-machine, because it's easier to read the "blup" when the X and Y have a s= taggered rising edge. A lot of this I'm making up as I go along. =

= ;

About= the seeding board, because of my lack of experience with bubble memory, are= all of the pins between the two sockets connected, except for the changes w= ith the 2N4013? I don't understand exactly how the bubble reservoir is made. However, I found the comman= ds and processes needed to get it going.

= ;

I lov= e your style of teaching. It's the same as mine. lol = ;I teach in the same fashion. However, I never found the video describ= ing how seeding is done. It's mentioned at the end or one of your videos, but I think you may never made it.

= ;

Paul<= /span>

= ;

From: SBC-85 <craig@sbc-85.com>
Sent: Tuesday, June 27, 2023 4:28 PM
To: Paul Holowko <p= holowko@hotmail.com>
Subject: Re: Your new user activation webpage is broken <= /o:p>

Hi Paul,

I completed a test registration yesterday and it d= id the same but it actually registered. I think I just need to add a. =E2= =80=9CThank yo7=E2=80=9D page. But the activation email worked at leas= t.

I am always interested in people using bubbles or t= hat have offshoots of some of my projects.

Have you gotten the bubble board up and running wi= th your micro code computer? Are you building the core and drivers from scra= tch or did you find some old core boards?

Regards

Craig

On Jun 27, 2023, at= 6:18 AM, Paul Holowko <pholowko@= hotmail.com> wrote:

=EF=BB=BF No, it goes to the same page for login a= nd says no errors.

BtY, I just completed laying out and stuffing a 1 M= eg bubble memory board. I=E2=80=99m using it for a micro code computer. In a= ddition Im putting together a stack of 4096 core memory X 8. I don=E2=80=99t= know if you have an interest in adding that to your website or even storing up conversations

Sent from my iPhone

On Jun 26, 2023, at= 5:16 PM, craig@sbc-85.com wrote:

=EF=BB=BF

Hi Paul

I have still not been able to figure out this pr= oblem, but I was able to manually activate your account. lets see if t= hat works. let me know if you still see a problem (or if there is anyt= hing specifically you are looking for).

regards

craig

From: Paul Holowko <pholowko@hotmail.com>
Sent: Saturday, April 8, 2023 8:37 AM
To: 052922@SBC-85.COM
Subject: Your new user activation webpage is broken